1. Field of the Invention
The invention relates to a method of controlling a clock signal in a circuit receiving an external clock signal and transmitting an internal clock signal. The invention relates also to a circuit for controlling a clock signal.
2. Description of the Related Art
A circuit for controlling a clock signal is generally comprised of a feedback system synchronization circuit such as phase locked loop, and is presently requested to eliminate clock skew in short synchronization time.
In order to meet with such request, a lot of circuits have been suggested in the following documents, for instance:
(a) Japanese Unexamined Patent Publication No. 8-237091
(b) 1996 Symposium on VLSI Circuit, pp. 112-113
(c) 1996 Symposium on VLSI Circuit, pp. 192-193
(d) Proceedings of IEEE 1992 CICC 25.2
(e) IEICE TRANS. ELECTRON, Vol. E79-C, No. 6, June 1996, pp. 798-807
(f) Japanese Unexamined Patent Publication No. 5-152438
(g) Japanese Unexamined Patent Publication No. 6-244282
FIGS. 1 to 6A and 6B illustrate circuits suggested in the above-listed prior art (a) to (e), respectively. As mentioned later in detail, the above-mentioned documents (a) to (g) do not suggest detecting clock delay unlike the present invention.
FIG. 1 illustrates a synchronization delay circuit having been suggested in Japanese Unexamined Patent Publication No. 8-237091.
The illustrated synchronization delay circuit is comprised of a synchronization delay circuit macro 908, an input buffer 903, a dummy delay circuit 905, and a clock driver 904. The synchronization delay circuit macro 908 is comprised of a first row of delay circuits 901 for measuring a time difference, and a second row of delay circuits 902 for reproducing the thus measured delay time. A clock signal is transmitted in the second row of delay circuits 902 in a direction opposite to a direction in which a clock signal is transmitted in the first row of delay circuits 901. The dummy delay circuit 905 is designed to have delay time equal to a sum (td1+td2) of delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904.
The dummy delay circuit 905 is usually comprised of an input buffer dummy 905A having the same structure and hence the same delay time as that of the input buffer 903, and a clock driver dummy 905B, in order to equalize the delay time thereof to a sum (td1+td2) of the delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904.
An external clock signal 906 is input into the first row of delay circuits 901 through the input buffer 903 and the dummy delay circuit 905, and output through the second row of delay circuits 902. The thus output clock signal is driven by the clock driver 904 to thereby turn into an internal clock signal 907, which is transmitted to internal circuits (not illustrated).
With reference to FIG. 1, the first row of delay circuits 901 has the same delay time as that of the second row of delay circuits 902. The first row of delay circuits 901 measures a certain period of time, and the second row of delay circuits 902 reproduces the thus measured period of time. A signal input into the first row of delay circuits 901 is advanced through the first row of delay circuits 901 by a desired period of time, and then, a signal is advanced in the second row of delay circuits 902 through the same number of delay devices as the number of delay devices through which the signal has passed in the first row of delay circuits 901. As a result, the second row of delay circuits 902 can reproduce a period of time having been measured by the first row of delay circuits 901.
Processes by which a signal is advanced in the second row of delay circuits 902 through the same number of delay devices as the number of delay devices through which the signal has passed in the first row of delay circuits 901 is grouped into two groups with respect to a direction or directions in which a signal is transmitted in the first and second rows of delay circuits 901 and 902. In addition, a length of the second row of delay circuits 902 is determined either by selecting an end of the length or by entirely selecting a row. Hence, the above-mentioned processes can be grouped into four groups.
For instance, as to the former grouping, each of FIGS. 4 and 5 illustrates a circuit in which a clock signal is advanced in the first row of delay circuits 901 in the same direction as a direction in which a clock signal is advanced in the second row of delay circuits 902, and the number of elements constituting the second row of delay circuits 902 is determined by an output terminal of the second row of delay circuits 902. Each of FIGS. 2 and 3 illustrates a circuit in which a clock signal is advanced in the first row of delay circuits 901 in a direction opposite to a direction in which a clock signal is advanced in the second row of delay circuits 902, and the number of elements constituting the second row of delay circuits 902 is determined by an input terminal of the second row of delay circuits 902.
As to the latter grouping, each of FIGS. 2 and 5 illustrates a circuit in which a length of the second row of delay circuits 902 is determined by selecting an end of the length, whereas each of FIGS. 3 and 4 illustrates a circuit in which a length of the second row of delay circuits 902 is determined by selecting an entire length.
FIG. 2 illustrates a circuit having been suggested in the above-listed document (a), FIG. 3 illustrates a circuit having been suggested in the above-listed document (e), FIG. 4 illustrates a circuit having been suggested in the above-listed document (c), and FIG. 5 illustrates a circuit having been suggested in the above-listed documents (b) and (d).
Hereinbelow is explained an operation for removing clock skew with reference to timing charts illustrated in FIGS. 6A, 6B, 7A, and 7B.
(A) Clock Delay in a Circuit Having no Synchronization Delay Circuits
FIG. 6A illustrates a circuit having no synchronization delay circuits. An external clock signal 906 is input through an input buffer 903, and is driven by a clock driver 904 to thereby turn into an internal clock signal 907. A delay time difference between the external clock signal 906 and the internal clock signal 907 is equal to a sum of delay time td1 of the input buffer 903 and delay time td2 of the clock driver 904. As illustrated in FIG. 6B, the sum (td1+td2) is clock skew in the illustrated circuit.
(B) Principle in Removal of Clock Delay by Means of a Synchronization Delay Circuit
A synchronization delay circuit removes clock skew, based on that a clock pulse is input thereinto every clock cycle tCK. Specifically, a delay circuit having delay time defined as (tCKxe2x88x92(td1+td2)) is positioned between an input buffer having delay time td1 and a clock driver having delay time td2, and is designed to have delay time equal to a clock cycle tCK (td1+tCKxe2x88x92(td1+td2)+td2=tCK). As a result, an internal clock signal transmitted from the clock driver has the same timing as that of an external clock signal.
(C) Removal of Clock Delay by Means of a Synchronization Delay Circuit
FIG. 7B is a timing chart of a synchronization delay circuit.
A synchronization delay circuit needs 2 clock cycles (2xc3x97tCK) to operate. In a first cycle, a synchronization delay circuit measures delay time (tCKxe2x88x92(td1+td2)) dependent on a clock cycle, and determines delay for a delay circuit which reproduces delay time (tCKxe2x88x92(td1+td2)). In a second cycle, the thus measured delay time (tCKxe2x88x92(td1+td2)) is used.
As illustrated in FIG. 7A, a dummy delay circuit 905 and a row of delay circuits 901 are used for measuring the delay time (tCKxe2x88x92(td1+td2)) dependent on a clock cycle, in the first cycle.
A first pulse in successive two pulses in an external clock signal 906 is input through an input buffer 903, and is transmitted through a dummy delay circuit 905 and a row of delay circuits 901 during a clock cycle tCK starting when the first pulse leaves the input buffer 903 and terminating when a second pulse leaves the input buffer 903. Since the dummy delay circuit 905 has delay time defined as (td1+td2), a period of time in which the external clock signal 906 is advanced through a first row of delay circuits 901 is defined as (tCKxe2x88x92(td1+td2)).
A second row of delay circuits 902 is designed to have delay time equal to the above-mentioned period of time (tCKxe2x88x92(td1+td2)) in which the external clock signal 906 is advanced through the first row of delay circuits 901.
The delay time of the second row of delay circuits 902 can be set in accordance with any one of the above-mentioned four processes.
In the second cycle, a clock signal transmitted from the input buffer 930 advances through the second row of delay circuits 902 having delay time defined as (tCKxe2x88x92(td1+td2)), and then, is output through the clock driver 904. Thus, there is produced an internal clock signal 907 having delay time tCK.
The thus produced internal clock signal 907 has a cycle of 2xc3x97tCK and has no clock skew.
However, the above-mentioned synchronization delay circuits are accompanied with the following problems.
The first problem is that since dummy delay of a clock signal is fixed, it is necessary to estimate fixed dummy delay in advance. It would be possible to design a dummy delay circuit for each one of chips in a device in which clock delay can be estimated in advance, such as a micro-processor and a memory device. However, it would be quite difficult to design a dummy delay circuit for such a device in which clock delay is dependent on wiring layout of a chip, as an application specific integrated circuit (ASIC).
The second problem is that, as illustrated in FIGS. 8A and 8B, there is a difference both in dependency of delay time on a temperature and in dependency of delay time on a source voltage between a clock driver and a clock driver dummy, and in addition, even in a device in which clock delay can be estimated in advance, such as a micro-processor and a memory device.
The third problem is that it is impossible to eliminate a delay time difference in an internal clock signal made synchronized with an external clock signal, as having been indicated in the above-mentioned document (e), because a delay circuit for measuring a delay difference and a delay circuit for reproduction are both accomplished by determining the number of stages in a delay circuit row, and further because there is a time difference in a period of time for charging and discharging between those delay circuits. This causes dependency of a delay error or a delay time difference inherent to a digital circuit, on a clock cycle.
The fourth problem is that it is necessary to entirely drive a row of delay circuits when a clock cycle is to be reproduced by means of the row of delay circuits, resulting in an increase in load capacity and an increase in current consumption.
In view of the foregoing problems of the conventional circuits, it is an object of the present invention to provide a method of controlling a clock signal, which is capable of detecting clock delay, preventing an increase in load capacity, and avoiding generation of delay error inherent to a digital circuit.
It is also an object of the present invention to provide a circuit for controlling a clock signal, which is capable of doing the same.
In one aspect of the invention, there is provided a method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, (c) stopping the external clock signal to be transmitted by the first period of time, and (d) driving the external clock signal to thereby turn the external clock signal into an internal clock signal.
It is preferable that a second period of time defined as (T1xe2x88x92(T2xe2x88x92Nxc3x97T1)) is calculated in the step (b), if T1 is smaller than T2, wherein N is an integer meeting with the equation T1 greater than (T2xe2x88x92Nxc3x97T1), and wherein the external clock signal is stopped to be transmitted by the second period of time in step (c).
In another aspect of the invention, there is provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, (c) a clock-delay compensator for stopping the external clock signal to be transmitted by the first period of time, and (d) a clock driver for driving the external clock signal to thereby turn the external clock signal into an internal clock signal.
It is preferable that the clock delay detector detects a second period of time defined as (T1xe2x88x92(T2xe2x88x92Nxc3x97T1)), if T1 is smaller than T2, wherein N is an integer meeting with the equation T1 greater than (T2xe2x88x92Nxc3x97T1), and wherein the compensator stops the external clock signal to be transmitted by the second period of time.
There is further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector receiving a first output clock signal transmitted from the input buffer, a second output clock signal transmitted from the clock-delay compensator, and a third output clock signal transmitted from the input buffer dummy to thereby detect the first period of time.
For instance, the clock delay detector may be comprised of a clock cycle detector for detecting a first clock cycle T1 of the first output clock signal, and a skew delay detector for detecting skew T2 in each of the input buffer and the clock driver, in which case, the skew delay detector may include (a) first and second delay generators for generating first and second output signals each having delay defined as (T1xe2x88x92T2+xcex1) for every 2xc3x97T1, based on signals having delay defined as (T1+xcex1) and obtained by dividing the first output clock signal, wherein xcex1 indicates a delay error inherent to a digital circuit, (b) a cycle delay generator for generating a third output signal having delay defined as (T1+xcex1) and delayed from the first output clock signal by T1, (c) a synthesizer for synthesizing output signals transmitted from the first and second delay generators, and (d) a timing difference detector for detecting a timing difference between an output signal transmitted from the synthesizer and an output signal transmitted from the cycle delay generator, the skew delay detector generating delay time (T1xe2x88x92T2), based on the timing difference, and activating the stop signal by a period of time equal to the delay time (T1xe2x88x92T2).
The clock delay detector may be comprised of a clock cycle detector for detecting a first clock cycle T1 of the first output clock signal, and a skew delay detector for detecting skew T2 in each of the input buffer and the clock driver, in which case, the skew delay detector may include (a) a delay generator for generating an output signal having delay defined as (T1xe2x88x92T2+xcex1) for every 2xc3x97T1, based on signals having delay defined as (T1+xcex1) and obtained by dividing the first output clock signal, wherein a indicates a delay error inherent to a digital circuit, (b) a cycle delay generator for generating a third output signal having delay defined as (T1+xcex1) and delayed from the first output clock signal by T1, (c) a multiplier for multiplying an output signal transmitted from the delay generator, by a certain number, (d) a timing difference detector for detecting a timing difference between an output signal transmitted from the synthesizer and an output signal transmitted from the multiplier, the skew delay detector generating delay time (T1xe2x88x92T2), based on the timing difference, and activating the stop signal by a period of time equal to the delay time (T1xe2x88x92T2).
It is preferable that each of the first and second delay generators is comprised of a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, a clock signal input into each of the first and second delay generators being looped at a position associated with the turned-on switch, and being transmitted in the delay circuits toward an output port.
For instance, the cycle delay generator may be comprised of a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, a clock signal input into the cycle delay generator being looped at a position associated with the turned-on switch, and being transmitted in the delay circuits toward an output port.
For instance, the clock cycle detector may be comprised of a plurality of delay circuits and a plurality of latch circuits, and wherein one of the latch circuits located at a position associated with one of the delay circuits where the first output clock signal reaches, transmits a signal indicative of the clock cycle T1, when a next first output clock signal is input thereto.
It is preferable that at least one of the first, second, and cycle delay generators is comprised of a plurality of MOS transistors at least one of which is turned on when receiving an output signal transmitted from the clock cycle detector, the first period of time being comprised of a period of time in which the turned-on MOS transistor is charged.
For instance, the period of time in which the turned-on MOS transistor is charged may be controlled by varying load capacity of the MOS transistor. As an alternative, the period of time in which the turned-on MOS transistor may be charged is controlled by varying a current supplied from a power source to the MOS transistor.
It is preferable that at least one of the first, second and cycle delay generators is comprised of a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, and wherein a clock signal input into the delay circuits is output from a delay circuit among the delay circuits, associated with the turned-on switch.
It is preferable that at least one of the first, second and cycle delay generators is comprised of a plurality of first delay circuits, a plurality of second delay circuits in which a clock signal is transmitted in a direction opposite to a direction in which a clock signal is transmitted in the first delay circuits, and a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, a clock signal input thereinto being transmitted through the first delay circuits, being input into the second delay circuits from a first delay circuit among the first delay circuits, located in association with the turned-on switch, through the turned-on switch, and being transmitted through the second delay circuits toward an output port thereof.
There is still further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector including (ba) a clock cycle detector for detecting a clock cycle of a first output clock signal transmitted from the input buffer, and (bb) a skew delay detector for skew delay in each of the input buffer and the clock driver, the skew delay detector including (bb1) a first timing difference detector for transmitting a clock signal having a pulse width indicative of a time difference defined as (td1+td2) wherein td1 indicates delay time of the input buffer and td2 indicates delay time of the clock driver, (bb2) a clock cycle detector dummy having the same delay time td3 as that of the clock cycle detector and receiving the first output clock signal, (bb3) a divider for dividing both the first output clock signal and an output clock signal transmitted from the clock cycle detector dummy to thereby transmit complementary clock signals each having a cycle of 2xc3x97T1 and a pulse width defined as (T1+td3), and each having a leading edge equal to that of the first output clock signal and a trailing edge delayed from that of the first output clock signal by td3, (bb4) first and second synthesizers for synthesizing the complementary clock signals and the clock signal transmitted from the first timing difference detector to thereby transmit output signals each having a cycle of 2xc3x97T1 and also having an active level period defined as (td1+td2+T1+td3), (bb5) first and second control gates each receiving the complementary clock signals to thereby be controlled as to receiving the first output clock signal, (bb6) first and second delay generators each including a plurality of switches one of which is turned on when receiving an output clock signal transmitted from the clock cycle detector, and a plurality of delay circuits, each of the first and second delay generators receiving both output clock signals transmitted from the first and second control gates and output clock signals transmitted from the first and second synthesizers, the output clock signals transmitted from the first and second control gates being controlled by the output clock signals transmitted from the first and second synthesizers as to advancing and stopping in the delay circuits, (bb7) a cycle delay generator including a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, the cycle delay generator receiving the first output clock signal, which is looped at a position associated with the turned-on switch, and is transmitted in the delay circuits toward an output port, (bb8) a third synthesizer for synthesizing output signals transmitted from the first and second delay generators, and (bb9) a second timing difference detector for detecting a difference between an output signal transmitted from the third synthesizer and an output signal transmitted from the cycle delay generator, and transmitting a signal indicative of the thus detected difference to the clock-delay compensator as the stop signal.
There is yet further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector including (ba) a clock cycle detector for detecting a clock cycle of a first output clock signal transmitted from the input buffer, and (bb) a skew delay detector for skew delay in each of the input buffer and the clock driver, the skew delay detector including (bb1) a first timing difference detector for transmitting a clock signal having a pulse width indicative of a time difference defined as (td1+td2) wherein td1 indicates delay time of the input buffer and td2 indicates delay time of the clock driver, (bb2) a divider for dividing the first output clock signal to thereby transmit complementary clock signals each having a cycle of 2xc3x97T1 and a pulse width defined as (T1+xcex1) where xcex1 indicates a delay error inherent to a digital circuit, and each having a leading edge equal to that of the first output clock signal and a trailing edge delayed from that of the first output clock signal by (T1+xcex1), (bb3) first and second synthesizers for synthesizing the complementary clock signals and the clock signal transmitted from the first timing difference detector to thereby transmit output signals each having a cycle of 2xc3x97T1 and also having an active level period defined as (td1+td2+T1+xcex1), and (bb4) a cycle delay generator including a plurality of switches one of which is turned on when receiving the first output clock signal, and a plurality of delay circuits, the cycle delay generator receiving the first output clock signal, which is looped at a position associated with the turned-on switch, and is transmitted in the delay circuits toward an output port, the clock delay compensator including (c1) first and second control gates each receiving the complementary clock signals to thereby be controlled as to receiving the first output clock signal, (c2) first and second delay generators each including a plurality of switches one of which is turned on when receiving an output clock signal transmitted from the clock cycle detector, and a plurality of delay circuits, each of the first and second delay generators receiving both output clock signals transmitted from the first and second control gates and output clock signals transmitted from the first and second synthesizers, the output clock signals transmitted from the first and second control gates being controlled by the output clock signals transmitted from the first and second synthesizers as to advancing and stopping in the delay circuits, and (c3) a third synthesizer for synthesizing output signals transmitted from the first and second delay generators, the thus synthesized output signals being transmitted to the clock driver.
There is still yet further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector including (ba) a clock cycle detector for detecting a clock cycle of a first output clock signal transmitted from the input buffer, and (bb) a skew delay detector for skew delay in each of the input buffer and the clock driver, the skew delay detector including (bb1) a first timing difference detector for transmitting a clock signal having a pulse width indicative of a time difference defined as (td1+td2) wherein td1 indicates delay time of the input buffer and td2 indicates delay time of the clock driver, (bb2) a clock cycle detector dummy having the same delay time td3 as that of the clock cycle detector and receiving the first output clock signal, (bb3) a divider for dividing both the first output clock signal and an output clock signal transmitted from the clock cycle detector dummy to thereby transmit complementary clock signals each having a cycle of 2xc3x97T1 and a pulse width defined as (T1+td3), and each having a leading edge equal to that of the first output clock signal and a trailing edge delayed from that of the first output clock signal by td3, (bb4) first and second synthesizers for synthesizing the complementary clock signals and the clock signal transmitted from the first timing difference detector to thereby transmit output signals each having a cycle of 2xc3x97T1 and also having an active level period defined as (td1+td2+T1+td3), (bb5) a control gate receiving the complementary clock signals to thereby be controlled as to receiving the first output clock signal, (bb6) a delay generator including a plurality of switches one of which is turned on when receiving an output clock signal transmitted from the clock cycle detector, and a plurality of delay circuits, the delay generator receiving both output clock signal transmitted from the control gate and output clock signals transmitted from the first and second synthesizers, the output clock signal transmitted from the control gate being controlled by the output clock signals transmitted from the first and second synthesizers as to advancing and stopping in the delay circuits, (bb7) a cycle delay generator including a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, the cycle delay generator receiving the first output clock signal, which is looped at a position associated with the turnedon switch, and is transmitted in the delay circuits toward an output port, (bb8) a multiplier for multiplying an output signal transmitted from the delay generator, by a certain number, and (bb9) a second timing difference detector for detecting a difference between an output signal transmitted from the multiplier and an output signal transmitted from the cycle delay generator, and transmitting a signal indicative of the thus detected difference to the clock-delay compensator as the stop signal.
It is preferable that at least one of the first, second and cycle delay generators is comprised of a plurality of MOS transistors at least one of which is turned on when receiving an output signal transmitted from the clock cycle detector, the first period of time being comprised of a period of time in which the turned-on MOS transistor is charged.
It is preferable that at least one of the first, second and cycle delay generators is comprised of a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, and wherein a clock signal input into the delay circuits is output from a delay circuit among the delay circuits, associated with the turned-on switch.
It is preferable that at least one of the first, second and cycle delay generators is comprised of a plurality of first delay circuits, a plurality of second delay circuits in which a clock signal is transmitted in a direction opposite to a direction in which a clock signal is transmitted in the first delay circuits, and a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, a clock signal input thereinto being transmitted through the first delay circuits, being input into the second delay circuits from a first delay circuit among the first delay circuits, located in association with the turned-on switch, through the turned-on switch, and being transmitted through the second delay circuits toward an output port thereof.
There is further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector including (ba) a clock cycle detector for detecting a clock cycle of a first output clock signal transmitted from the input buffer, and (bb) a skew delay detector for skew delay in each of the input buffer and the clock driver, the skew delay detector including (bb1) a first timing difference detector for transmitting a clock signal having a pulse width indicative of a time difference defined as (td1+td2) wherein td1 indicates delay time of the input buffer and td2 indicates delay time of the clock driver, (bb2) a clock cycle detector dummy having the same delay time td3 as that of the clock cycle detector and receiving the first output clock signal, (bb3) a divider for dividing both the first output clock signal and an output clock signal transmitted from the clock cycle detector dummy to thereby transmit complementary clock signals each having a cycle of 2xc3x97T1 and a pulse width defined as (T1+td3), and each having a leading edge equal to that of the first output clock signal and a trailing edge delayed from that of the first output clock signal by td3, (bb4) first and second synthesizers for synthesizing the complementary clock signals and the clock signal transmitted from the first timing difference detector to thereby transmit output signals each having a cycle of 2xc3x97T1 and also having an active level period defined as (td1+td2+T1+td3), (bb5) a timing signal generator for generating a timing signal having a duty ratio of 50, (bb6) a delay generator including a plurality of switches one of which is turned on when receiving an output clock signal transmitted from the clock cycle detector, and a plurality of delay circuits, the delay generator receiving both an output clock signal transmitted from the timing signal generator and output clock signals transmitted from the first and second synthesizers, the output clock signal transmitted from the timing signal generator being controlled by the output clock signals transmitted from the first and second synthesizers as to advancing and stopping in the delay circuits, (bb7) a cycle delay generator including a plurality of switches one of which is turned on when receiving an output signal transmitted from the clock cycle detector, and a plurality of delay circuits, the cycle delay generator receiving the first output clock signal, which is looped at a position associated with the turned-on switch, and is transmitted in the delay circuits toward an output port, (bb9) a second timing difference detector for detecting a difference between an output signal transmitted from the delay generator and an output signal transmitted from the cycle delay generator, and transmitting a signal indicative of the thus detected difference to the clock-delay compensator as the stop signal.
There is further provided a circuit for controlling a clock signal, including (a) an input buffer through which an external clock signal is received, (b) a clock delay detector for detecting a first period of time defined as (T1xe2x88x92T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, and transmitting a stop signal by the first period of time, (c) a clock-delay compensator for receiving the stop signal from the clock delay detector and stopping the external clock signal to be transmitted by the first period of time, (d) a clock driver for driving an output signal transmitted from the clock-delay compensator to thereby turn the output signal into an internal clock signal, and (e) an input buffer dummy equivalent to the input buffer for receiving the internal clock signal, the clock delay detector including (ba) a clock cycle detector for detecting a clock cycle of a first output clock signal transmitted from the input buffer, and (bb) a skew delay detector for skew delay in each of the input buffer and the clock driver, the skew delay detector including (bb1) a first timing difference detector for transmitting a clock signal having a pulse width indicative of a time difference defined as (td1+td2) wherein td1 indicates delay time of the input buffer and td2 indicates delay time of the clock driver, (bb2) a divider for dividing the first output clock signal to thereby transmit complementary clock signals each having a cycle of 2xc3x97T1 and a pulse width defined as (T1+xcex1) where xcex1 indicates a delay error inherent to a digital circuit, and each having a leading edge equal to that of the first output clock signal and a trailing edge delayed from that of the first output clock signal by (T1+xcex1), (bb3) first and second synthesizers for synthesizing the complementary clock signals and the clock signal transmitted from the first timing difference detector to thereby transmit output signals each having a cycle of 2xc3x97T1 and also having an active level period defined as (td1+td2+T1+xcex1), and (bb4) a cycle delay generator including a plurality of switches one of which is turned on when receiving the first output clock signal, and a plurality of delay circuits, the cycle delay generator receiving the first output clock signal, which is looped at a position associated with the turned-on switch, and is transmitted in the delay circuits toward an output port, the clock delay compensator including (c1) a timing signal generator for generating a timing signal having a duty ratio of 50, and (c2) a delay generator including a plurality of switches one of which is turned on when receiving an output clock signal transmitted from the clock cycle detector, and a plurality of delay circuits, the delay generator receiving both output clock signal transmitted from the timing signal generator and output clock signals transmitted from the first and second synthesizers, the output clock signal transmitted from the timing signal generator being controlled by the output clock signals transmitted from the first and second synthesizers as to advancing and stopping in the delay circuits.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.